Semiconductor memory devices are comprised of at least one array of memory cells. Each memory cell is comprised of a capacitor, on which the charge stored represents the logical state of the memory cell. A positive charged capacitor corresponds to a logical state of “1” and a negative capacitor corresponds to a logical state of “0.” Word lines activate access transistors, so that the logical state of a memory cell can be read. Gates of multiple transistors are formed as one word line.
An example of a word line's application is in a dynamic random access memory (DRAM). In a DRAM, a common word line, used to access memory cells, is fabricated on a p-type silicon substrate coated with a thin film of silicon dioxide (SiO2), known as gate oxide. Then, a word line is formed on the gate oxide layer.
The performance of the DRAM, and the small device sizes that are achievable are largely dependent on the resistance of the DRAM circuitry. There are inherent resistances in the conducting materials chosen for the circuits, and there are resistances due to the configuration of the circuits. Even though a low resistance metal may be chosen for a conductor, the size of the cross section of a conductor affects its resistivity, and neighboring structures may create a capacitance that causes additional resistance in the conductor. The combination of these effects in a circuit can be measured by a constant called a resistance-capacitance (RC) time constant. A lower resistance in the circuit leads to a lower value of the RC time constant, and a faster performing memory device.
The RC time constant is especially affected by wordline design due to the extended length of word lines, and their necessarily small size as they are integrated into access transistors. In ultra large scale integrated (ULSI) circuits, a highly conductive word line is necessary to improve circuit density and performance. It therefore follows, that the problem of wordline RC losses must be overcome. As devices are scaled down in size, word line widths are also decreased. Both the smaller cross section of wordlines, and the increased length of wordlines in ULSI circuits contribute to increased resistance. To date, word line resistance is one of the primary limitations of achieving faster ULSI circuits. A method for decreasing the resistivity of word lines is needed for use in ULSI applications.
Wordlines are frequently made of polysilicon, however polysilicon has a relatively high resistivity compared to other metal materials. One approach to lowering wordline resistivity has been to add a second layer of lower resistivity metal on top of a polysilicon wordline to make a two layer wordline. The aim of this approach is to lower the resistivity of the entire wordline, and as a result to accommodate the large number of memory cells that a wordline must access in a ULSI circuit. A significant problem with this approach has been the compatibility of the polysilicon with the second metal layer. They tend to diff use into each other, and the low resistivity of the metal layer is drastically compromised.
What is needed is a DRAM wordline design that lowers the RC time constant of the circuit without the diffusion problems associated with multiple metal layers in wordline design.